IYM Technologies LLC is a technology licensing company that owns a four-patent portfolio – as well as a pending patent application – that covers technology for the improved design and layout of integrated circuits.
For the efficient manufacture of semiconductor devices, certain design rules must be followed to ensure the operation of devices manufactured on the semiconductor substrate. For a given manufacturing process, a set of design rules are applied during chip layout to avoid geometry patterns that would result in chip failure. These design rules are engineered to maximize the functionality of the devices on the semiconductor wafer (the yield) while minimizing the footprint of the devices.
With the ever-decreasing size of semiconductor devices, the size and placement of these devices is critical. If two neighboring devices are placed too close to each other, the risk of a malfunction increases due to the inability to correctly manufacture a particular device and/or electrical interference from neighboring devices. This will, in turn, affect the yield of operable devices on the silicon substrate. As a consequence, more and more design rules are required in order to maintain the yield as the concentration of devices per unit area increases.
The patents in IYM Technologies’ portfolio teach a method for improving the desired layout. By utilizing local process modification of the layout design, a designer may address local issues according to the specific characteristics of design and manufacturing conditions, allowing him to improve the resultant layout.
In addition to the above, another innovative concept covered by this portfolio is the concept of rules interdependence (rules localization in the patentee’s lexicography). In the areas where there are many elements that are borderline violating design rules, there is need to make the design rules stronger to avoid defects.